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Chapter 5 Synchronous sequential design - 副本

发布时间:2014-01-14 09:01:15  

Summery:
Sequence statements: IF,CASE,WAIT,NULL, FOR_LOOP Concurrent statements: WITH-SELECT,WHEN-ELSE, PROCESS, BLOCK, component, port map Classical combinational circuit: Decoder, Encoder,Multiplex,Adder, Parity checker,Three-state buffer

Chapter 5 Synchronous sequential design
Information processing unit ——For transmission and operation Digital of the information. system Control unit ——control the processing order
FSM 、control register、Microcode controller (Finite state machine)

5.1 Synchronous sequential system
Combinational logic : The outputs depend on the Digital system
present values of inputs, not the previous values or states.

Sequential logic : The outputs depend on the present
values of inputs and the past values or states. outputs Combination logic Present state next state inputs

Register

5.1 Synchronous sequential system
Sequential logic Synchronous : Controlled by a clock. Asynchronous
Q1 =1 D clk Q D Q Q0

Q1

Q0

D clk

Q

D

Q

Dff clk nQ

Dff clk nQ

Dff clk nQ

Dff clk nQ

Synchronous circuit

Asynchronous circuit

5.1 Synchronous sequential system

Synchronous circuit

Asynchronous circuit

5.2 Moore and Mealy machines
State state. machine Mealy: the outputs are function of the present state
and of the inputs.
State register inputs Next state logic Clock Moore machine outputs Output logic

Moore: the outputs are solely function of the present

inputs

Next state logic Clock

State register

outputs Output logic

Mealy machine

Mealy machines
Design a simple controller for a set of traffic signals:
Major road

G R

0 5 4 3 2 1
Minor road

Car/Start_timer CAR Major=G Minor=R Timed Major=R Minor=G Timed

Algorithmic state machines
The ASM chart for the traffic signal controller
G
MAJOR=GRN MINOR=RED

G X=1 Y

1011 J 1

0

Z =1

CAR

0
State Box

1
START_TIMER

Decision Box Conditional Output Box

R
MAJOR=GRN MINOR=RED

1

TIMED

0

Note: The ASM charts represent physical hardware, therefore all transitions within the chart must form closed paths --- hardware cannot suddenly start or stop except a reset state.

Algorithmic state machines

The difference between state box and condition box
Z Z

c

1
0
Y

c

1 0
Y

W

W

ASM(a)

ASM(b)

Conditional and unconditional outputs

Clock

Z 1

ASM(a): Z

c 0 W

Y,C=1
Y Y,C=0 W

ASM(a)

ASM(b): Z

C tested here

Z c 0 W 1 Y

Y,C=1 W,C=1 Y,C=0 W,C=0

ASM(b)

Hardware implementation
An ASM chart describes what a system does but not how it is done. So the ASM chart is expressed as a more compact state and output table which contains the same information.

Method 1: Digital logic circuit
G
MAJOR=GRN MINOR=RED

CAR

0

Present state G R

Car, timed 00 01 11 10

1
START_TIMER

G,0 G,0 R,0 G,0

R,1 R,1 G,0 R,0

R
MAJOR=GRN MINOR=RED

Next state, start_timer

1

TIMED

0

Car, timed Q 0 1 00 0,0 1,0 01 0,0 0,0 11 1,1 0,0 10 1,1 1,0

Qn+1, start_timer

Qn+1:
CAR, TIME

START_TIMER:
CAR, TIMED

A 0 1

00 0 1

01 0 0

11 1 0

10 1 1

A 0 1

00 0 0

01

0 0

11 1 0

10 1 0

k-maps for traffic signal controller

Expression can be derived for the state variable and the output.
Q n?1 ? Q ? CAR ? Q ? TIMED START _ TIMER ? Q ? CAR

Timed
Car

&
≥1

&

Clock

D Q DFF C Q

Start_timer

Method 2: VHDL LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY traffic IS PORT (clock, timed, car: IN std_logic; start_timer,major_green,minor_green : OUT std_logic); END ;

Single process
ARCHITECTURE asm1 OF traffic IS BEGIN PROCESS(clock) IS TYPE state_type IS ( G, R ); VARIABLE state: state_type; BEGIN start_timer<='0';

The Start_timer signal is given a default value at the beginning of the process in order to prevent the synthesizer producing a latch.

CASE state IS WHEN G => major_green <= '1';minor_green <= '0'; IF car = '1' THEN start_timer<='1';state :=R; END IF; WHEN R => major_green <= '0'; minor_green <= '1'; IF timed = '1' THEN state:=G; END IF; END CASE; WAIT UNTIL clock='1'; END PROCESS; END asm1;

Double processes:
For sequential states
Code of state machine

Describe the state-changing controlled by the clock.
For combinational logic Describe the outputs and the statechanging conditions for every state.

Two SIGANL type objects which represent the current state and the next state are used to transmit information between two processes.

ENTITY traffic IS PORT (clock, timed, car: IN std_logic; start_timer,major_green,minor_green : OUT std_logic); END ; ARCHITECTURE asm2 OF traffic IS TYPE state_type IS ( G, R ); VARIABLE state : state_type; BEGIN

Seq: PROCESS (clock) IS BEGIN IF clock’EVENT and clock=‘1’ THEN Present_state<=next_state; END IF; END PROCESS seq;

When the rising edge occur, the value of the “next_state” will transfer to the “present_state”. Even if the state is no change, the value of “next_state” must be updated, otherwise a latch will be produced with synthesizing.

com:PROCESS(car,timed,present_state) BEGIN case语句对 Start_timer<=’0’; present_state 作出选 CASE present_state IS 择并更新next_state WHEN G => major_green <= '1'; minor_green <= '0'; IF car = '1' THEN start_timer<='1'; next_state<=R; ELSE next_state<=G; END IF; WHEN R => major_green <= '0'; minor_green <= '1'; IF timed = '1' THEN next_state<=G; ELSE next_state<=R; END IF; END CASE; END PROCESS com;

Three processes 把次态ns和输出op逻辑块分开
ns:PROCESS(car,timed,present_state) IS BEGIN CASE present_state IS WHEN G => IF car = '1' THEN next_state<=R; ELSE next_state<=G; END IF; WHEN R => IF timed = '1' THEN next_state<=G; ELSE next_state<=R; END IF; END CASE; END PROCESS ns;

op:PROCESS (car, present_state) BEGIN Start_timer<='0'; IF present_state=G THEN major_green <= '1'; minor_green <= '0'; IF car = '1' THEN start_timer<='1'; END IF; ELSE major_green <= '0'; minor_green <= '1'; END IF; END PROCESS op;

OP process can be described with combinational statements, as the following: start_timer<=’1’ WHEN (present_state=G AND car=’1’) ELSE ‘0’;

major_green <=’1’ WHEN (present_state=G’) ELSE ‘0’; minor_green <=’1’ WHEN (present_state=R ) ELSE ‘0’;

Attention: If multi-process is adopted, must sure that there is only combinational logic in the combinational process and there is only one edge-sensitive signal in sequential process.

Moore machines
Vending machine

Design a vending machine for drinking. It is 40 cents per tin. Only 20-cent and 10-cent are accepted by the machine. Once 40 cents are put in, the drinking will be delivered. If more than 40 cents are put in, all the coins will be return. There are two lights in this system, one of them presents the next sealing is ready and the other one represents more coins is needed.

A:sealing-ready and no coin is put in. B:10 cents are accepted. C:20 cents are accepted. D:30 cents are accepted. E:return all the coins and turn to A state F:drinking-dispensing then turn to A state

E/ret twenty A/Ready twenty C/coin ten ten ten twenty B/coin twenty D/coin ten F/dispense

The state keeps, if no coin is put in under A, B, C or D state.

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY vending IS PORT (clock,reset,twenty,ten: IN STD_LOGIC; ready,dispense,ret,coin: OUT STD_LOGIC); END vending; ARCHITECTURE asm OF vending IS TYPE STATE_TYPE IS (A,B,C,D,E,F); SIGNAL present_state,next_state: STATE_TYPE; BEGIN …… END asm;

seq:PROCESS (clock,reset) BEGIN IF reset = '1' THEN present_state <= A; ELSIF rising_edge(clock) THEN present_state <= next_state; END IF; END PROCESS seq;

com:PROCESS (twenty,ten,present_state) BEGIN ready<='0'; dispense<='0'; ret<='0'; coin<='0'; CASE present_state IS …… …… END CASE; END PROCESS com;

WHEN A => ready<='1'; IF ten ='1' THEN next_state <= B; ELSIF twenty ='1' THEN next_state <= C; ELSE next_state <= A; END IF;

WHEN B => coin<='1'; IF ten ='1' THEN next_state <= C; ELSIF twenty ='1' THEN next_state <= D; ELSE next_state <= B; END IF;

WHEN C => coin<='1'; IF ten ='1' THEN next_state <= D; ELSIF twenty ='1' THEN next_state <= F; ELSE next_state <= C; END IF;

WHEN D => coin<='1'; IF ten ='1' THEN next_state <= F; ELSIF twenty ='1' THEN next_state <=E; ELSE next_state <= D; END IF;

WHEN E=> ret<='1'; next_state <= A; WHEN F => dispense<='1'; next_state <= A;

Sequential detector
Design a state machine with the following state transition. Must has a asynchronous reset port in this circuit.
1/0 0/0 1/0 S0 0/0 S1 1/0 S2 0/0 1/1 0/0 S3

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY machine IS PORT (d, clk, rst: IN STD_LOGIC; z: OUT STD_LOGIC); END machine; ARCHITECTURE behave OF machine IS TYPE state_type IS (s0, s1, s2, s3); SIGNAL present_state, next_state: state_type; BEGIN ┆ END behave;

P1: PROCESS( clk, rst) BEGIN IF rst=’0’ THEN present_state<=s0; co<=’0’; ELSIF clk’ EVENT AND clk=’1’ THEN present_state<=next_state; END IF; END PROCESS p1;

P2: PROCESS(present_state,d) BEGIN CASE present_state IS ┆ END CASE; END PROCESS p2;

WHE

N s0 => IF d=’0’ THEN next_state<=s1; ELSIF d=’1’ THEN next_state<=s0; END IF; z<=’0’; WHEN s1 => IF d=’0’ THEN next_state<=s1; ELSIF d=’1’ THEN next_state<=s2; END IF; z<=’0’;

WHEN s2 => IF d=’0’ THEN next_state<=s3; ELSIF d=’1’ THEN next_state<=s0; END IF; z<=’0’; WHEN s3 => IF d=’0’ THEN next_state<=s1; z<=’0’; ELSIF d=’1’ THEN next_state<=s2; z<=’1’; END IF;


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